Module Catalogues, Xi'an Jiaotong-Liverpool University   
 
Module Code: EEE201
Module Title: CMOS Digital Integrated Circuits
Module Level: Level 2
Module Credits: 2.50
Academic Year: 2019/20
Semester: SEM1
Originating Department: Electrical and Electronic Engineering
Pre-requisites: EEE203 MTH007 MTH008 MTH013 MTH101 MTH102 MTH201
   
Aims
To combine CMOS integrated circuit design exercises with very relevant industrial concepts and a deeper understanding of MOSFET device physics principles and electromagnetism.


To provide the background for later modules, relevant final year projects, but particularly for employment in those industries that are firmly based in microelectronics technology.


To further develop the concept of design as being more than simple problem solving, but something demanding high levels of innovation based on sound physics principles.

Learning outcomes 
A. Demonstrate knowledge and understanding of CMOS-based integrated circuit design with considerations of power, speed, yield, packing density and design trade-offs associated with material, device and circuit limitations.

B. Demonstrate knowledge of historical and future development of silicon-based integrated circuit technology.

C. Apply knowledge of integrated circuit technology to determine design considerations when working with CMOS integrated circuits.

D. Analyse and design simple CMOS logic gates.

E. Demonstrate the ability to apply physics to engineering design.

F. Develop independent learning, problem solving and design skill.

Method of teaching and learning 
This module will be delivered through a combination of lectures (which are embedded with short tutorial topics on the integrated circuit design after teaching MOSFET as switch) and supervised laboratory sessions.

Syllabus 
1. Properties of silicon: basic quantum mechanics, E-k diagram, energy gap, conductivity and carrier mobility.


2. Simple two terminal devices: MOS capacitor and p-n junction; built-in potential and capacitance.


3. MOSFET switch: basic operation, inverter and its static and dynamic behaviours; voltage transfer characteristics, noise margins.


4. CMOS combinational logic circuits: NAND and NOR gates; realisation of more complex combinational logic gates, speed and power dissipation.


6. CMOS physical layout design: intuitive understanding of device operation with different physical structures; interconnect and effects of its capacitance and resistance; fabrication-based layout principles and area minimisation; drawing skills; report presentation skills


7. Advanced CMOS digital integrated circuits: pseudo N-MOS and dynamic logic principles; domino logic and its principles, advantages and disadvantages; memory structures

Delivery Hours  
Lectures Seminars Tutorials Lab/Prcaticals Fieldwork / Placement Other(Private study) Total
Hours/Semester 26      8    41  75 

Assessment

Sequence Method % of Final Mark
1 Assignments 5.00
2 In-Class Short Quizzes 10.00
3 Cmos Ic Design Project 15.00
4 Final Exam 70.00

Module Catalogue generated from SITS CUT-OFF: 5/23/2019 5:32:51 AM