Module Catalogues, Xi'an Jiaotong-Liverpool University   
 
Module Code: EEE337
Module Title: Integrated Circuits – Concepts and Design
Module Level: Level 3
Module Credits: 5.00
Academic Year: 2019/20
Semester: SEM1
Originating Department: Electrical and Electronic Engineering
Pre-requisites: EEE201 AND EEE205 EEE201
   
Aims
This module aims to familiarise students with some basic concepts of silicon based microelectronics, IC technology, and IC design by using a professional design tool; to prepare students for entering the Si semiconductor industry.
Learning outcomes 
A. Gain the knowledge of how to analyse, design and lay-out simple MOS integrated circuits (ICs).

B. Understand silicon IC technology and theoretical underpinning.

C. Understand fabrication steps and related manufacturing issues for MOS-based IC design.

D. Use a professional design tool (Tanner Tools) to design, layout and test by simulation digital circuit cells and show the experience and enhancement of the IC design skills.

E. Understand fundamental design issues for silicon IC's taking into account manufacturing limitations.

Method of teaching and learning 
This module will be delivered through a combination of formal lectures, tutorials and both supervised and unsupervised laboratory (CMOS IC design) sessions.
Syllabus 
Week 1
Lecture 1: Review of the MOST-transistor physics and models, plus design considerations.

Lecture 2: CMOS inverters

Review of CMOS fabrication processes. Layout and design rules, Latch up and transient response. Model for parasitics in a CMOS inverter. Effect on transient response. Calculation of delay time.


Week 2
Lecture 3: Introduction to Assignment 1(Assignment 1 hand-in, week4).

Matlab/C program transient response calculations of a CMOS inverter.

Tutorial 1 (Assignment 1): Transient response calculation of a CMOS inverter.


Week 3
Lecture 4: Historical Evolution of MOS logic families with circuit analysis.

Resistor, saturated and unsaturated MOST load, depletion load (nMOS) technologies: basic inverter operation advantages and disadvantages of each. Size scaling.

Lecture 5: CMOS circuits, Static NAND & NOR gates, Combinational logic, fan-out, JK flip-flop.


Week 4
Lecture 6: Introduction to Assignment 2(Assignment 2 hand-in, week6).

Introduction to Tanner Tools-walk through 1-10 of CMOS inverter transient response and power dissipation of CMOS inverters.

Tutorial 2 (Assignment 2): Tanner Tools: L-Edit, DRC, T-Spice, W-Spice.


Week 5
Lecture 7: Introduction to Assignment 3 (Assignment 3 hand-in, week8).

Investigate effects of capacitive load on transient response and power of dissipation of a 2-input NAND and JK flip-flop.
Tutorial 3 (Assignment 3): Design of a CMOS 2-input NAND gate and JK flip-flop.


Week 6
Lecture 8: Introduction to Assignment 4 (Assignment 4 hand-in, week 10).

Investigate effects of parasitics, design of a Master-Slave JK flip-flop, and design of a decade counter.

Tutorial 4 (Assignment 4): Design of Master-Slave JK flip-flop and decade counter.


Week 7
Lectures 9-10: Dynamic CMOS circuits.

nMOS and CMOS transfer gates, shift register, pre-charge concept and domino logic, design issues: charge sharing, charge coupling and de
Delivery Hours  
Lectures Seminars Tutorials Lab/Prcaticals Fieldwork / Placement Other(Private study) Total
Hours/Semester 40     12  24    74  150 

Assessment

Sequence Method % of Final Mark
1 Assignment 1 - Transient Response Calculation Of A Cmos Inverter 10.00
2 Assignment 2 - Design Of Cmos Inverters 10.00
3 Assignment 3 - Design Of 2-Input Nand Gate And Jk Flip-Flop 15.00
4 Assignment 4 - Design Of Master-Slave Jk Flip-Flop And Decade Counter 15.00
5 Final Exam 50.00

Module Catalogue generated from SITS CUT-OFF: 5/23/2019 5:41:59 AM