Aims and Fit of Module

To provide students with the ability to:
- Design and synthesise digital systems using HDL.
- Understand the problems of meta-stability in digital systems.
- Design and synthesise microsprocessor systems using HDL
- Develop and test System on a Programmable Chips (SOPC) design using Altera NIOS

Learning outcomes

A. Acquire the knowledge of the HDL language for synthesis, the use of the Library of Parameterised Modules (LPM) and the capabilities of the HDL language for simulation.
B. Understand the design issues when generating complex digital systems (including microprocessors).
C. Apply the knowledge of the module topics to the synthesis of a stable and robust digital system using HDL in order to simulate and synthesise a RISC microprocessor, and implement a SOPC design.
D. Obtain the experience and practical skills in the use of CAE tools for designing, synthesising and simulating digital systems.

Method of teaching and learning

This module will be delivered through a combination of formal lectures, tutorials and both supervised and unsupervised laboratory sessions.